Complementary metal-oxide-semiconductor (CMOS) design is the key technology of mainstream digital electronics that allows ultra-high levels of integration to be achieved by greatly reducing power dissipation. Low-power complementary circuits (with or without an oxide technology) are well suited for battery-powered systems such as portable display devices and multi-element sensor networks, as well as for radio-frequency identification tags with extended operating range. Such circuits can also be critical for military technologies including analog-to-digital and digital-to-analog conversion for applications such as radar and distributed autonomous sensing and communication.
From an implementation standpoint, CMOS is superbly well served by the Si/SiO2 material system. It provides nearly matching mobilities for electrons and holes and the ability to withstand high temperature processing, allowing one to fabricate the requisite n-channel and p-channel transistors within a single layer of Si simply by doping the source/drain regions (as contacts) and channels (for threshold control) appropriately.
In contrast, the III-V compound antimonide-based semiconductors are nowhere near as suitable for use in CMOS structures. If materials with different lattice constants and/or crystalline structures are used (e.g. Ge and InGaAs), then the integration becomes more complex. For example, selective regrowth of InGaAs on Ge has been envisioned, but has previously been difficult to achieve. Moreover, the electron and hole mobilities of III-V materials are markedly different, limiting their usefulness as n- and p-channel FETs in a single device. In addition, they require low-temperature processing, which greatly limits the strategies available for doping.
Nevertheless, the tremendous potential benefits for power dissipation and speed presented by the III-V semiconductors have motivated various efforts aimed at overcoming these challenges and exploring the feasibility of III-V materials for use in CMOS structures. See R. Chau et al., “Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications,” IEEE Transactions on Nanotechnology 4, 153 (2005); B. R. Bennett et al., “Antimonide-based compound semiconductors for electronic devices: A review,” Solid State Electronics 49, 1875 (2005); R. Kiehl et al., “p-Channel FET Based on p/n Double-Quantum-Well Heterostructure,” IEEE Electr. Device Lett. 10, 42 (1989); A. Leuther et al., Complementary HFETS on GaAs with 0.2 μm gate length, 26th Int'l Symp. Compound Semiconductors 1999, pp. 313-316 (2000); T. Tsai et al., “Characteristics of InGaP/InGaAs complementary pseudomorphic doped-channel HFETs,” Solid-State Electronics 52, 146 (2008); and R. B. Brown et al., “Overview of Complementary GaAs Technology for High-Speed VLSI Circuits,” IEEE Trans. on VLSI Systems, 6, 47 (1998). Achieving the use of III-V materials in CMOS devices may allow microprocessors to follow Moore's Law for additional generations.
Efforts have been made to improve electron mobility in the antimonides. For example, graded buffer layers on InP substrates have been used to achieve n-channel-In0.5Ga0.5Sb quantum wells with room-temperature mobilities of 19,000 cm2/V·S. See G. Delhaye et al., “Metamorphic high electron mobility Te-doped AlInSb/GaInSb heterostructures on InP (001),” J. Appl. Phys. 104, 066105 (2008). N-channel-InSb FETs have also been investigated, with mobilities of 25,000 cm2/V-s and excellent high-frequency FET performance being achieved. See S. Datta et al., “85 nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications,” Electron Devices Meeting, 2005, IEDM Technical Digest. IEEE International, pp. 763-766, 5 Dec. 2005. p-InSb-channel FETs also have been achieved. See M. Radosavljevic et al., “High-Performance 40 nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (VCC=0.5V) Logic Applications,” IEEE International Electron Devices Meeting 2008, Technical Digest, 727.
In addition, it has previously been shown that hole mobility in the antimonides can be improved by increasing the strain in the quantum well acting as the transport channel. See B. R. Bennett, et al., “Mobility enhancement in strained p-InGaSb quantum wells,” Applied Physics Letters 91, 042104 (23 Jul. 2007). B. R. Bennett et al., “Strained GaSb/AlAsSb quantum wells for p-channel field-effect transistors,” J. Crys. Growth 311, 47 (2008); and M. Radosavljevic et al., supra. It may also be possible to achieve higher hole mobilities without sacrificing electron mobility by, for example, reducing the thickness of the quantum well and possibly increasing the InSb mole fraction. See B. R. Bennett et al., Appl. Phys. Lett., supra. Other groups are pursuing InGaAs for the n-channel material and strained Ge for the p-channel material, see, e.g., D. Lin et al., “Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution,” IEDM 2009, 327-330 (2009), but these materials have different crystalline structures and lattice constants, making their integration a significant challenge.
Ultimately, which of the antimonide-based materials turns out to be best suited for complementary logic circuit technology will depend not just on the electron and hole mobilities, but also on a host of other factors such as scalability, contact resistance, drive and leakage currents, integrability with oxides/dielectrics, and enhancement-mode capability. M. G. Ancona, et al. “Scaling Projections for Sb-Based p-Channel FETs,” Solid-State Electronics 54, 1349-1358 (November 2010).
In previous work with GaAs, InGaAs, and InAs/GaSb channels, separate layers were grown for the n- and p-channels. See, e.g., K. F. Longenbach et al., “A Complementary Heterostructure Field Effect Transistor Technology Based on InAs/AISb/GaSb,” IEEE Trans. Electron Dev. 37, p. 2265, 1990; and A. Leuther et al., supra.